1. Field of the Invention
The present invention relates to a semiconductor memory device having redundancy memory cells and, particularly, to an address detector of a redundancy memory cell.
2. Description of the Related Art
In a semiconductor memory device having redundancy memory cells, when a defective memory cell is detected, the defective memory cell is replaced with a redundancy memory cell. The technique of redundancy thus improves the yield of such semiconductor devices.
Replacement of a defective memory cell with a redundancy cell is normally performed using a cell array column unit or a cell array row unit. Accordingly, the semiconductor memory device is provided with a plurality of redundancy columns or rows. Specifically, when an address corresponding to the column or to the row including a defective cell is input to the semiconductor memory device, selection of the column or the row including the defective cell is prohibited, and a redundancy column or row to replace respective column or row having the defective cell must instead be selected. In order to accomplish this, the redundancy circuit must have a means to store address information, or a programming element, to replace a defective memory cell with a redundancy cell.
Commonly, the programming element is a fuse which is fused, or melted, by laser. However, with the prior art techniques, it was impossible for an address detector of redundancy cells to access a redundancy cell before a defective memory cell was detected, the address was determined, and the appropriate fuse was fused.
In the case where a polysilicon fuse is used as a programming element, the fuse may be blown electrically. This raises difficult design concerns because a large current must then be supplied to the IC circuit to blow the fuse.
In some non-volatile semiconductor memory devices, an EPROM cell may be used as a programming element instead of a fuse. In this case, however, data stored in a defective address memory element is erased by radiation of ultraviolet rays. Therefore, the EPROM cell must be structured so as not to be irradiated by unwanted ultraviolet rays. In order to accomplish this, the area occupied by the memory cell must be increased, however, an increase in area is unfavorable to the design of an IC circuit.
In the prior art wafer probe test, only when a defective memory cell was found, was the defective cell subject to a substitution process, so that the probe test could not be performed on the redundancy cell when all of the memory cells were in normal operating condition. Thereby, as the integration density of semiconductor memory devices increases, the prior art probe test used in the manufacture of these devices becomes increasingly unsatisfactory because it is complicated, time-consuming and costly.
Japanese patent application No. 61-136838 addresses the above problem by providing that during a test mode a redundancy cell is selected and normal cell is non-selected. In this case, however, reading and writing to the redundancy cell can be performed only during the test mode. Also, only a specific address can be used to select the redundancy cell. Moreover, the address of the address detector in the test mode differs from that of the address detector that is eventually used.